A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR

Recently, PAM4^*1 signaling has been used instead of conventional NRZ^*2 signaling to meet the demand for high-speed data communications. In addition, an ADC^*3-DSP^*4 based receiver has also been used instead of an analog-based receiver for enabling digital equalization to handle high insertion loss channel with high data rate. Most ADC-DSP based receivers use baud-rate^*5 CDR^*6 such as Mueller-Müller CDR, while most analog-based receivers use the 2x oversampling CDR. However, in the conventional baud-rate CDR circuits, the clock signal is occasionally locked at false-lock points as a result of misjudging specific transitions between data 0 and 3 as whole transitions of the PAM-4 signaling (Figure 1).

We discovered that the clock signal is locked at the correct point when the comparator for the CDR is operated in the NRZ mode even if the PAM4 signaling is input. Therefore, the false–lock points can be avoided by using the comparator for the CDR in the NRZ mode (Figure 2). The comparator for the CDR is first operated in the NRZ mode and then the parameters of the equalizers, variable-gain amplifiers, and the comparators for the CDR and data-path are adaptively controlled. Next, the clock signal is successfully recovered from the PAM4 input signal. After that, the comparator for the CDR is changed to the PAM4 mode and the parameters of the equalizers and comparators are optimized again and the clock signal is adjusted properly.

The die micrograph of the fabricated chip is shown in Figure 3. The chip is fabricated in a 16-nm FinFET process. When measuring the fabricated receiver, 56-Gb/s PAM4 signaling is generated in the transmitter and then input into the receiver via an external cable. By using the proposed false-lock-aware locking technique, the PAM4 signaling is correctly received even when the clock signal is locked at the false-lock point initially (Figure 4).